(1) Field of the Invention
The invention relates to a method of etching improved contact openings to DRAM peripheral circuits and more particularly to the formation of the dielectric interlevel layers in such a way to allow the etching of contact openings having superior slope characteristics.
(2) Description of the Prior Art
It is recognized in the integrated circuit technology that contact openings must have a satisfactory slope which allows the subsequent complete filling of the openings with metal for proper electrical contact of the regions in the semiconductor wafer. The problem is becoming increasingly more difficult as the feature size, that is the width of the openings is getting smaller.
There has been great progress in the development of DRAM integrated circuits over the recent years. The stacked capacitor has been particularly improved so as to maintain the desired capacitance while still reducing the dimensions of the cell array. Examples of improvements in stacked capacitors can be understood by reference to U.S. Pat. No. 5,110,752 by C. Y. Lu and to U.S. Pat. No. 5,126,916 to H. H. Tseng.
However, with this important DRAM progress in the cell array portion of the integrated circuit there have resulted problems, particularly in the peripheral circuits wherein the needs of the cell array for interlevel dielectric compositions between the metallurgy levels have impacted the etching of electrical contact openings. The preferred interlevel dielectric has become a first layer of silicon oxide and a second layer of borophosphosilicate glass (BPSG). The BPSG is used so that it can be flowed at reasonably high temperatures for planarization and to round sharp corners at, for example contact openings. Where there are two levels of interlevel dielectric layer, as is common over the peripheral circuits etching of contact openings at smaller feature sizes have become unsatisfactory due to surface tension bulges of the BPSG layers. This results in negative slope in the etched openings which in turn makes it nearly impossible to completely fill the openings with metal conductor material using the simple and preferred metal deposition processes, such as sputtering.
It is an object of this invention to provide methods to overcome the DRAM peripheral circuit contact opening negative slope problem without using complex metallurgy or etching processes.
It is a further object of this invention to provide a method which improves the etching of electrical contact openings in the peripheral circuits of a DRAM structure by critically specifying the order of layers within the two interlevel dielectric layers through which the contact openings are to be etched.